The circuit of the present invention relates generally to motor control circuits and more particularly to fault detection circuits incorporated therein. It is known to utilize motor driver circuits to interface a microcomputer or other controller with motor power drive apparatus so as to control electrical motor operation. It is also known to utilize an H-bridge transistor configuration and pulse width modulation (PWM) operation in driving reversible multi-phase motors. The H-bridge transistor configuration provides a pair of series connected switching transistors which are alternatively driven to a conducting condition so as to connect each phase of the motor to the supply side of the power source or to ground for driving the motor in either of the forward or reverse directions.
In carrying out the control operations associated with sequentially connecting the phases of a motor to a power source, it is necessary to avoid damage to the switching transistors and to the multi-phase motor. Fault detection circuitry has been included in prior art motor driver interface circuits such as U.S. Pat. No. 5,111,123 (Hach et al). The circuit disclosed in Hach monitors the voltage drop across a two phase motor's phase windings to detect faulty motor operation. On the occurrence of a fault condition, the Hach circuit disables the transistor gate drive signals, and thereby prevents current flow through the motor and the switching transistors. Fault detection circuitry has also been provided in motor driver interface circuits to provide "off" mode fault detection when the transistor gates have been deactivated. One of the shortcomings associated with many prior art fault detection circuits is that they only function in brushed DC motor applications.
To avoid start-up transient and spurious fault indication, it is necessary to provide a fault detection circuit with a mask time delay feature. This time delay feature prevents the fault detection circuit from acknowledging a fault condition until a predetermined number of clock pulses, which represent a corresponding calculated period of time, have been counted. The necessary time delay period is dependent upon the particular load characteristics of the motor to be controlled. A major shortcoming of prior art fault detection circuits is their inability to adjust the duration of the mask time delay period. Accordingly, prior art fault detection circuit configurations, once selected, only function for a certain fixed range of loads. Therefore, such circuits can only be used with certain motors.
What is needed is a fault detection circuit for use in motor control apparatus which functions in either brushed or brushless motor applications.
A fault detection circuit is also needed that can provide a programmably adjustable fault mask time delay for allowing the same circuit to be used with a wide range of motors.